If working properly, the user should have two separate program windows.

Cadence Virtuoso by typing virtuoso in the terminal window. At the end of this tutorial the user should be. Running LVS on both views to verify that they have the same.The purpose of this tutorial is to introduce students to using Cadence Design Tools for the use in the design, simulation, and layout of a typical CMOS inverter. Importing the Verilog netlist into a schematic in Cadence Composer. Importing the place-and-route layout to Cadence Virtuoso. If working properly, the user should have two separate program windows open (the Cadence Log Window and the Cadence Overview Window), similar to the figure below: Basic Cadence Virtuoso Tutorial on creating a NOR Gate's Schematic, Symbol and Layout. The user can now run Cadence Virtuoso by typing virtuoso in the terminal window. If working properly, the user should have two separate program windows open (the Cadence Log Window and the Cadence Overview Window), similar to the figure below: using Cadence effectively, but is not necessary to the completion of this tutorial. After you hit 'OK', Virtuoso screen will appear as shown below (in addition, LSW window with various mask layers will automatically pop up): using Cadence effectively, but is not necessary to the completion of this tutorial. Hit 'Enter', following window will pop up: Select 'Virtuoso' tool, View Name is automatically set to 'layout'.

Simply type in 'nand2' under cell name and 'layout' under view.

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